Programmable read-only memory (PROM) chips are well known and widely used in a variety of computer devices. A conventional PROM chip includes a grid of metal conductors forming columns and rows. The columns and rows are formed on different layers of the chip, separated by a dielectric layer, and initially include conductive fuses interconnecting each row/column intersection. Each intersection provides one bit. To program the chip, a relatively high current is selectively routed to certain fuses to cause them to burn out. Intersections where fuses remain have a value of 1, while those where the fuses have been burned out provide a value of 0 in the binary logic of the circuit.
Modified types of PROM chips are also known. Negative-channel metal-oxide semiconductor (NMOS) chips have been developed that allow bits to be addressed individually, rather than in an array, and use different fuse technology. Such non-standard PROM chips are used in ink jet printheads and the like. Notwithstanding differences with standard PROM technology, NMOS chips are programmed and used in basically the same way. Fuses are selectively burned out to program each bit to the desired binary state.
Programming and using ROM chips in this way has some drawbacks. If a chip is improperly programmed initially, there is no way to fix it, and the chip must be discarded. Additionally, fuses are relatively large, and can be unreliable. In ink jet printhead circuits, for example, fuses can damage the ink jet orifice layer during programming, and after a fuse burns out, metal debris from the fuse can be drawn into the ink and cause blockage in a pen, or result in poor quality printing.
In recent years, electronically programmable read-only memory (EPROM) devices have also been developed. Unlike typical PROM chips, EPROM chips do not include fuses. Like typical ROM chips, EPROMs include a conductive grid of columns and rows. The cell at each intersection has two gates that are separated from each other by a thin oxide layer that acts as a dielectric. One of the gates is called a floating gate and the other is called a control gate or input gate. The floating gate's only link to the row is through the control gate. A blank EPROM has all of the gates fully open, giving each cell a value of 1. That is, the floating gate initially has no charge, which causes the threshold voltage to be low.
To change the value of the bit to 0, a programming voltage (e.g. 10 to 16 volts) is applied to the control gate and drain. This programming voltage draws excited electrons to the floating gate, thereby increasing the threshold voltage. The excited electrons are pushed through and trapped on the other side of the thin oxide layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate. During use of the EPROM cell, a cell sensor monitors the threshold voltage of the cell. If the threshold voltage is low (below the threshold level), the cell has a value of 1. If the threshold voltage is high (above the threshold level), the cell has a value of zero.
Because EPROM cells have two gates at each intersection, an EPROM chip requires additional layers compared to a standard NMOS or PROMchip. Consequently, while some of the drawbacks of fuses in NMOS circuits could be eliminated by the application of EPROM circuitry to the same application, the use of EPROM cells either requires that the chip be provided with additional layers, which increases the cost and complexity of the chip, or that a separate EPROM chip be provided.